Integrated circuits with multiple low dielectric-constant inter-metal dielectrics

ABSTRACT

The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics. An integrated circuit structure is formed having a substrate; an inorganic layer on the substrate which is composed of a pattern of metal lines on the substrate and an inorganic dielectric on the substrate between the metal lines; and an organic layer on the inorganic layer which is composed of an organic dielectric having metal filled vias therethrough which connect to the metal lines of the inorganic layer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the formation of structures inmicroelectronic devices such as integrated circuit devices. Moreparticularly, the invention relates to the formation of vias,interconnect metallization and wiring lines using multiple lowdielectric constant intermetal dielectrics.

[0003] 2. Description of the Related Art

[0004] In the production of microelectronic devices, integrated circuitsutilize multilevel wiring structures for interconnecting regions withindevices and for interconnecting one or more devices within theintegrated circuits. In forming such structures, it is conventional toform a first lower level wiring lines, then an interlevel dielectriclayer and then to form second level wiring lines. One or more metalfilled vias are typically formed in the interlevel dielectric to connectthe first and second level wiring lines.

[0005] One conventional method for forming a two level wiring structureis to first form a two level interconnect structure over a substrate.The surface of a substrate may be the surface of a silicon devicestructure or the surface of substrate may be an insulating layer. Anoxide layer is typically deposited over the substrate by chemical vapordeposition. The first level interconnect structures are defined by aconventional photolithography process which forms openings through theoxide layer where the first level interconnects will be formed.Generally, the openings expose portions of conductors in the substrateto which interconnects are formed. The openings are filled with a metalinterconnect to form the interconnect and form a metal plug. Then alayer of metal such as aluminum is deposited over the surface of theoxide layer and over the metal plug to a thickness appropriate forsecond level wiring lines. The metal layer is then patterned into thesecond level wiring lines. The second level wiring lines are defined ina conventional photolithography process by providing a layer ofphotoresist over the metal layer, exposing the photoresist through amask and removing portions of the exposed photoresist layer to form aphotoresist etch mask. The portions of the metal layer exposed byopenings in the photoresist mask are then removed by etching and thephotoresist mask is removed by ashing. After the two level interconnectstructure is formed, it is necessary to provide an intermetal dielectric(IMD) layer between the second level wiring lines and covering thesecond level wiring lines to accommodate further processing of theintegrated circuit device. In the past, the intermetal dielectric layermight consist of one or more layers of oxide deposited by plasmaenhanced chemical vapor deposition or other processes.

[0006] Prior art integrated circuits produced by single or dualdamascene processes with Cu interconnects and low dielectric-constant(k) intermetal dielectrics have used only one kind of low-k dielectric,either inorganic, organic or a hybrid of these two kinds. Thisconventional approach of using the same kind of low-k dielectric forboth metal-level and via-level IMD has limited process integration andimplementation options. As a result, additional processing steps andadded cost are required. It is desirable whenever possible to reduce thenumber of processing steps required to form a device because reducingthe number of processing steps shortens the time required to produce thedevice and because eliminating processing steps improves yields and soreduces costs.

[0007] The present invention uses two or more dissimilar low-kdielectrics for the intermetal dielectrics of Cu-based dual damascenebackends of integrated circuits. The use of both organic and inorganiclow-k dielectrics offers several advantages due to the significantlydifferent plasma etch characteristics of these two kinds of dielectrics.One dielectric serves as an etchstop in etching the other dielectric. Noadditional oxide or nitride etchstop layer is required. High performanceis achieved due to the lower parasitic capacitance resulting from theuse of low-k dielectrics.

SUMMARY OF THE INVENTION

[0008] The invention provides an integrated circuit structure whichcomprises a substrate and (a) an inorganic layer on the substrate whichcomprises a pattern of metal lines on the substrate and an inorganicdielectric on the substrate between the metal lines; and (b) an organiclayer on the inorganic layer which comprises an organic dielectrichaving metal filled vias therethrough which connect to the metal linesof the inorganic layer. Preferably the integrated circuit structurecomprises (c) an additional inorganic layer on the organic layer whichcomprises a pattern of additional metal lines on the organic layer andan inorganic dielectric on the organic layer between the additionalmetal lines; and (d) an additional organic layer on the additionalinorganic layer which comprises an organic dielectric having metalfilled vias therethrough which connect to the additional metal lines ofthe additional inorganic layer.

[0009] The invention also provides an integrated circuit structure whichcomprises a substrate and (a) an organic layer on the substrate whichcomprises a pattern of metal lines on the substrate and an organicdielectric on the substrate between the metal lines; and (b) aninorganic layer on the organic layer which comprises an inorganicdielectric having metal filled vias therethrough which connect to themetal lines of the organic layer. Preferably the integrated circuitstructure comprises (c) an additional organic layer on the inorganiclayer which comprises a pattern of additional metal lines on theinorganic layer and an organic dielectric on the inorganic layer betweenthe additional metal lines; and (d) an additional inorganic layer on theadditional organic layer which comprises an inorganic dielectric havingmetal filled vias therethrough which connect to the additional metallines of the additional organic layer.

[0010] The invention also provides a dielectric coated substrate whichcomprises:

[0011] (a) a first dielectric composition film on a substrate; and

[0012] (b) a second dielectric composition film on the first dielectriccomposition film;

[0013] wherein the first dielectric composition and the seconddielectric composition have substantially different etch resistance.

[0014] The invention further provides a process for producing anintegrated circuit structure which comprises

[0015] (a) providing a substrate which comprises a pattern of metallines on the substrate and a dielectric on the substrate between themetal lines;

[0016] (b) depositing an organic dielectric layer on the substrate;

[0017] (c) depositing an inorganic dielectric layer on the organicdielectric;

[0018] (d) etching a pattern of vias through the inorganic dielectriclayer;

[0019] (e) etching a pattern of vias through the organic dielectriclayer which correspond to the pattern of vias through the inorganicdielectric layer;

[0020] (f) applying a photoresist to the top of the inorganic dielectriclayer and filling the vias in the organic dielectric layer and theinorganic dielectric layer with photoresist;

[0021] (g) imagewise removing a portion of the photoresist from the topof the inorganic dielectric layer; and removing a portion and leaving aportion of the photoresist through a thickness of the inorganicdielectric layer;

[0022] (h) removing part of the inorganic dielectric layer underlyingthe portions of the photoresist removed from the top of the inorganicdielectric layer to form trenches in the inorganic dielectric layer;

[0023] (i) removing the balance of the photoresist from the top of theinorganic dielectric layer and from the vias;

[0024] (j) filling the vias in the organic dielectric and the trenchesin the inorganic dielectric with a metal.

[0025] The invention still further provides a process for producing anintegrated circuit structure which comprises

[0026] (a) providing a substrate, which comprises a pattern of metallines on the substrate and a dielectric on the substrate between themetal lines;

[0027] (b) depositing an organic via level dielectric on the substrate;

[0028] (c) depositing an thin inorganic dielectric layer on the organicvia level dielectric;

[0029] (d) imagewise patterning and removing a portion of the thininorganic dielectric layer thus defining vias through the thin inorganicdielectric layer;

[0030] (e) depositing a thin organic dielectric etchstop material layeron the thin inorganic dielectric layer and filling the vias in the thininorganic dielectric layer with the organic dielectric material;

[0031] (f) depositing a metal level inorganic dielectric layer on theorganic dielectric etchstop layer;

[0032] (g) imagewise patterning and removing a portion of the metallevel inorganic dielectric layer down to the organic dielectric etchstopmaterial layer to form trenches in the metal level inorganic dielectriclayer;

[0033] (h) removing the portion of the organic dielectric etchstopmaterial layer underlying the corresponding removed portion of the metallevel inorganic dielectric to form trenches therein, and removing theorganic etchstop material from the vias in the thin inorganic dielectriclayer;

[0034] (i) removing the portion of the organic via level dielectriclayer underlying the thin inorganic dielectric layer thus forming viasthrough the organic via level dielectric layer down to the metal lines;

[0035] (j) filling the vias in the via level organic dielectric layerand the thin inorganic dielectric layer, and trenches in the organicdielectric etchstop layer and metal level inorganic dielectric layerwith a metal.

[0036] The invention also provides a process for producing an integratedcircuit structure which comprises

[0037] (a) providing a substrate, which comprises a pattern of metallines on the substrate and a dielectric on the substrate between themetal lines;

[0038] (b) depositing an organic via level dielectric layer on thesubstrate;

[0039] (c) depositing an thin inorganic dielectric layer on the organicvia level dielectric;

[0040] (d) depositing a thin organic dielectric etchstop material layeron the thin inorganic dielectric layer;

[0041] (e) depositing a metal level inorganic dielectric layer on theorganic dielectric etchstop layer;

[0042] (f) imagewise patterning and removing a portion of the metallevel inorganic dielectric layer down to the organic dielectric etchstopmaterial layer to form vias in the metal level inorganic dielectriclayer;

[0043] (g) removing the portion of the organic dielectric etchstopmaterial layer underlying the corresponding removed portions of themetal level inorganic dielectric layer to form vias in the organicdielectric etchstop material layer;

[0044] (h) removing the portion of the thin inorganic dielectric layerunderlying the corresponding removed portions of the organic dielectricetchstop material layer to form vias in the thin inorganic dielectriclayer;

[0045] (i) covering the top of the metal level inorganic dielectriclayer with a photoresist and filling the vias in the metal levelinorganic dielectric layer, the organic dielectric etchstop materiallayer and the thin inorganic dielectric layer with photoresist;

[0046] (j) imagewise patterning and removing a portion of thephotoresist from the top of the metal level inorganic dielectric layer;and removing a portion and leaving a portion of the photoresist througha thickness of the metal level inorganic dielectric layer;

[0047] (k) removing part of the metal level inorganic dielectric layerunderlying the portions of the photoresist removed from the top of theinorganic dielectric layer to form trenches in the metal level inorganicdielectric layer;

[0048] (l) removing the balance of the photoresist from the top of themetal level inorganic dielectric layer and from the vias; and removingthe portion of the organic dielectric etchstop material layer underlyingthe trenches until the thin inorganic dielectric layer is reached;

[0049] (m) removing the portion of the organic via level dielectriclayer underlying the vias in the thin inorganic dielectric layer;

[0050] (n) filling the vias in the via level organic dielectric layerand the thin inorganic dielectric layer, and trenches in the organicdielectric etchstop layer and metal level inorganic dielectric layerwith a metal.

[0051] The invention furthermore provides a process for producing anintegrated circuit structure which comprises

[0052] (a) providing a substrate, which comprises a pattern of metallines on the substrate and a dielectric on the substrate between themetal lines;

[0053] (b) depositing an organic via level dielectric layer on thesubstrate;

[0054] (c) depositing an thin inorganic dielectric layer on the organicvia level dielectric

[0055] (d) depositing a thin organic dielectric etchstop material layeron the thin inorganic dielectric layer;

[0056] (e) depositing a metal level inorganic dielectric layer on theorganic dielectric etchstop layer;

[0057] (f) imagewise patterning and removing a portion of the metallevel inorganic dielectric layer down to the organic dielectric etchstopmaterial layer to form vias in the metal level inorganic dielectriclayer;

[0058] (g) removing the portion of the organic dielectric etchstopmaterial layer underlying the corresponding removed portions of themetal level inorganic dielectric layer to form vias in the organicdielectric etchstop material layer;

[0059] (h) removing the portion of the thin inorganic dielectric layerunderlying the corresponding removed portions of the organic dielectricetchstop material layer to form vias in the thin inorganic dielectriclayer;

[0060] (i) removing the portion of the organic via level dielectriclayer underlying the corresponding removed portions of the thininorganic dielectric layer to form vias in the organic via leveldielectric layer;

[0061] (j) covering the top of the metal level inorganic dielectriclayer with a photoresist and filling the vias in the metal levelinorganic dielectric layer, the organic dielectric etchstop materiallayer, the thin inorganic dielectric layer and the organic via leveldielectric layer with photoresist;

[0062] (k) imagewise patterning and removing a portion of thephotoresist from the top of the inorganic dielectric layer; and removinga portion and leaving a portion of the photoresist through a thicknessof the metal level inorganic dielectric layer;

[0063] (l) removing part of the metal level inorganic dielectric layerunderlying the portions of the photoresist removed from the top of theinorganic dielectric layer to form trenches in the metal level inorganicdielectric layer;

[0064] (m) removing the balance of the photoresist from the top of themetal level inorganic dielectric layer and from the vias; and removingthe portion of the organic dielectric etchstop material layer underlyingthe trenches until the thin inorganic dielectric layer is reached;

[0065] (n) filling the vias in the via level organic dielectric layerand the thin inorganic dielectric layer, and trenches in the organicdielectric etchstop layer and metal level inorganic dielectric layerwith a metal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0066]FIG. 1 shows a first integrated circuit architecture ofmulti-level interconnections fabricated according to this invention.

[0067]FIG. 2 shows a second integrated circuit architecture ofmulti-level interconnections fabricated according to this invention.

[0068]FIG. 3 shows the formation process for a first embodiment of theinvention resulting after organic low-k dielectric deposition; inorganiclow-k dielectric deposition and resist spin and bake.

[0069]FIG. 4 shows the formation process resulting after via mask andresist development and metal trench inorganic low-k dielectric etch.

[0070]FIG. 5 shows the process result after via organic low-k dielectricetch.

[0071]FIG. 6 shows the process result after resist spin and bake.

[0072]FIG. 7 shows the result after metal trench mask and resistdevelopment.

[0073]FIG. 8 shows the result after inorganic low-k dielectric etch.

[0074]FIG. 9 shows the result after selective removal of resist.

[0075]FIG. 10 shows the result after Cu interconnect processing.

[0076]FIG. 11 shows the formation process for a second embodiment of theinvention resulting after organic low-k dielectric deposition; inorganiclow-k dielectric deposition and resist spin and bake.

[0077]FIG. 12 shows the formation process for a second embodiment aftervia mask and resist development and inorganic low-k dielectric etch.

[0078]FIG. 13 shows the process after resist removal.

[0079]FIG. 14 shows the process after organic low-k dielectricdeposition, inorganic low-k dielectric deposition, resist spin and bakeand metal trench mask and resist development.

[0080]FIG. 15 shows the process after inorganic low-k dielectric etch.

[0081]FIG. 16 shows the process after organic low-k dielectric etch.

[0082]FIG. 17 shows the process after organic low-k dielectric etch

[0083]FIG. 18 shows the second embodiment process after Cu interconnectprocessing.

[0084]FIG. 19 shows a third embodiment of the invention after organiclow-k dielectric deposition, inorganic low-k dielectric deposition,organic low-k dielectric deposition, inorganic low-k dielectricdeposition and resist spin and bake.

[0085]FIG. 20 shows the process after via mask and resist developmentand inorganic low-k dielectric etch.

[0086]FIG. 21 shows the process result after organic low-k dielectricetch and inorganic low-k dielectric etch.

[0087]FIG. 22 shows the process result after selective resist removal.

[0088]FIG. 23 shows the process result after resist spin and bake.

[0089]FIG. 24 shows the process result after metal trench mask andresist development.

[0090]FIG. 25 shows the process result after inorganic low-k dielectricetch.

[0091]FIG. 26 shows the process result after organic low-k dielectricetch.

[0092]FIG. 27 shows the process result after via inorganic low-kdielectric etch.

[0093]FIG. 28 shows a fourth embodiment of the invention after organiclow-k dielectric etch.

[0094]FIG. 29 shows the process result after resist spin and bake.

[0095]FIG. 30 shows the process result after metal trench mask andresist development.

[0096]FIG. 31 shows the process result after inorganic low-k dielectricetch.

[0097]FIG. 32 shows the process result after organic low-k dielectricand resist etch.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0098] The integrated circuit architecture produced by a first processembodiment of the invention is show in FIG. 1. This structure uses twodifferent kinds of low-k dielectric thin films for the IMD, onedielectric is organic and the other dielectric is inorganic. Shown inFIG. 1, architecture I, is the part of the backend of an integratedcircuit of multi-level interconnections fabricated according to thisinvention. An organic low-k dielectric is used for via-level IMD and aninorganic low-k dielectric is used for metal-level IMD. The architectureII, structure is produced according to another embodiment of theinvention. Architecture II differs from architecture I in that two thinlayers of low-k dielectrics, the top one organic and the bottominorganic, are added in between via-level and metal-level IMD. Theprocess steps used for the fabrication of via 1 and metal 2 can berepeated again for the upper levels of vias and metals. In the manyembodiments of the invention, alternating dieleectric layers have is asignificant difference in etch rate. The invention takes advantage of asignificant difference in plasma etch rate between organic and inorganicdielectrics. This is not available when the same dielectric is employedfor both via-level and metal-level IMD□. In oxygen-based plasmas,organic dielectrics etch tremendously faster than inorganic dielectrics.Inversely, in carbon fluoride based plasmas, inorganic dielectrics etchmuch faster than organic dielectrics.

[0099] A first process embodiment of the invention is exemplified byFIGS. 3 through 10. These figures show the process flow after theformation of the first-level interconnect or Metal 1, and the processflow from Via 1 level through the second level of interconnect or Metal2. However, the same processing steps can be repeated again for upperlevels of vias and interconnects. FIG. 3 shows the interim structureafter step 1 which is a deposition of an organic low-k dielectric, step2 which is a deposition of an in organic low-k dielectric and depositionand baking of a photoresist. The organic low-k dielectric is applied toa substrate having a pattern of metal lines on its surface. Typicalsubstrates include those suitable to be processed into an integratedcircuit or other microelectronic device. Suitable substrates for thepresent invention non-exclusively include semiconductor materials suchas gallium arsenide (GaAs), germanium, silicon, silicon germanium,lithium niobate and compositions containing silicon such as crystallinesilicon, polysilicon, amorphous silicon, epitaxial silicon, and silicondioxide (SiO₂) and mixtures thereof. The lines are typically formed bywell known lithographic techniques. Suitable materials for the linesinclude aluminum, aluminum alloys, copper, copper alloys, titanium,tantalum, and tungsten. These lines form the conductors of an integratedcircuit. Such are typically closely separated from one another atdistances preferably of from about 20 micrometers or less, morepreferably from about 1 micrometer or less, and most preferably of fromabout 0.05 to about 1 micrometer.

[0100] The organic and inorganic dielectric compositions may compriseany of a wide variety of dielectric forming materials which are wellknown in the art for use in the formation of microelectronic devices.The dielectric layers may nonexclusively include silicon containingspin-on glasses, i.e. silicon containing polymer such as an alkoxysilanepolymer, a silsesquioxane polymer, a siloxane polymer; a poly(aryleneether), a fluorinated poly(arylene ether), other polymeric dielectricmaterials, nanoporous silica or mixtures thereof. The only criteria forthis invention is that organic dielectrics are formed adjacent toinorganic dielectrics. Useful organic dielectrics are those which followwhich are carbon containing and inorganics are those which follow whichare not carbon containing.

[0101] One useful polymeric dielectric material useful for the inventioninclude an nanoporous silica alkoxysilane polymer formed from analkoxysilane monomer which has the formula:

[0102] wherein at least 2 of the R groups are independently C₁ to C₄alkoxy groups and the balance, if any, are independently selected fromthe group consisting of hydrogen, alkyl, phenyl, halogen, substitutedphenyl. Preferably each R is methoxy, ethoxy or propoxy. Such arecommercially available from AlliedSignal as Nanoglass™. The mostpreferred alkoxysilane monomer is tetraethoxysilane (TEOS). Also usefulare hydrogensiloxanes which have the formula[(HSiO_(1.5))_(x)O_(y)]_(n), hydrogensilsesquioxanes which have theformula (HSiO_(1.5))_(n), and hydroorganosiloxanes which have theformulae [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n),[(HSiO_(1.5))_(x)(RSiO_(1.5))_(y)]_(n) and[(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n). In each of these polymerformulae, x=about 6 to about 20, y=1 to about 3, z=about 6 to about 20,n=1 to about 4,000, and each R is independently H, C_(1 to C) ₈ alkyl orC₆ to C₁₂ aryl. The weight average molecular weight may range from about1,000 to about 220,000. In the preferred embodiment n ranges from about100 to about 800 yielding a molecular weight of from about 5,000 toabout 45,000. More preferably, n ranges from about 250 to about 650yielding a molecular weight of from about 14,000 to about 36,000. Usefulpolymers within the context of this invention nonexclusively includehydrogensiloxane, hydrogensilsesquioxane, hydrogenmethylsiloxane,hydrogenethylsiloxane, hydrogenpropylsiloxane, hydrogenbutylsiloxane,hydrogentert-butylsiloxane, hydrogenphenylsiloxane,hydrogenmethylsilsesquioxane, hydrogenethylsilsesquioxane,hydrogenpropylsilsesquioxane, hydrogenbutylsilsesquioxane,hydrogentert-butylsilsesquioxane and hydrogenphenylsilsesquioxane andmixtures thereof. Useful organic polymers include polyimides,fluorinated and nonfluorinated polymers, in particular fluorinated andnonfluorinated poly(arylethers) available under the tradename FLARE™from AlliedSignal Inc., and copolymer mixtures thereof. Thehydroorganosiloxanes, poly(arylene ethers), fluorinated poly(aryleneethers) and mixtures thereof are preferred, Suitable poly(aryleneethers) or fluorinated poly(arylene ethers) are known in the art fromU.S. Pat. Nos. 5,155,175; 5,114,780 and 5,115,082. Preferredpoly(arylene ethers) and fluorinated poly(arylene ethers) are disclosedin U.S. patent application Ser. No. 08/990,157 filed Dec. 12, 1997 whichis incorporated herein by reference. Preferred siloxane materialssuitable for use in this invention are commercially available fromAlliedSignal Inc. under the tradename Accuglass® T-11, T-12 and T-14.Also useful are methylated siloxane polymers available from AlliedSignalInc. under the tradenames Purespin™ and Accuspin® T18, T23 and T24.

[0103] Preferred silicon containing dielectric resins include polymershaving a formula selected from the group consisting of[(HSiO_(1.5))_(x)O_(y)]_(n),(HSiO_(1.5))_(n),[(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5)) _(z)]_(n),[(HSiO_(1.5))_(x)(RSiO_(1.5))_(y)]_(n) and[(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n) wherein x=about 6 to about20, y=1 to about 3, z=about 6 to about 20, n=1 to about 4,000, and eachR is independently H, C_(1 to C) ₈ alkyl or C₆ to C₁₂ aryl which aredisclosed in U.S. patent application Ser. No. 08/955,802 filed Oct. 22,1997 and which is incorporated herein by reference. Also preferred arecertain low organic content silicon containing polymers such as thosehaving the formula I:

[H—SiO_(1.5)]_(n)[R—SiO_(1.5)]_(m),

[H_(0.4)—SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)—SiO_(1.5-1.8)]_(m),

[H_(0-1.0)—SiO_(1.5-2.0)]_(n)[R—SiO_(1.5)]_(m),

[H—SiO_(1.5)]_(x)[R—SiO_(1.5)]_(y)[SiO₂]_(z),

[0104] wherein the sum of n and m, or the sum or x, y and z is fromabout 8 to about 5000, and m and y are selected such that carboncontaining substituents are present in an amount of less than about 40Mole percent. Polymers having the structure I are of low organic contentwhere the carbon containing substituents are present in an amount ofless than about 40 mole percent. These polymers are described more fullyin U.S. patent application Ser. No. 09/044,831, filed Mar. 20, 1998,which is incorporated herein by reference. Also preferred are certainhigh organic content silicon containing polymers such as those havingthe formula II:

[HSiO_(1.5)]_(n)[RSiO_(1.5)]_(m),

[H_(0.4-1.0)SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)SiO_(1.5-1.8)]_(m),

[H_(0-1.0)SiO_(1.5-2.0)]_(n)[RSiO_(1.5)]_(m),

[0105] wherein the sum of n and m is from about 8 to about 5000 and m isselected such that the carbon containing substituent is present in anamount of from about 40 mole percent or greater; and

[HSiO_(1.5)]_(x)[RSiO_(1.5)]_(y)[SiO₂]_(z);

[0106] wherein the sum of x, y and z is from about 8 to about 5000 and yis selected such that the carbon containing substituent is present in anamount of about 40 mole % or greater; and wherein R is selected fromsubstituted and unsubstituted straight chain and branched alkyl groups,cycloalkyl groups, substituted and unsubstituted aryl groups, andmixtures thereof. The specific mole percent of carbon containingsubstituents is a function of the ratio of the amounts of startingmaterials. Polymers having the structure II which are of high organiccontent where the carbon containing substituents are present in anamount of about 40 mole percent or more. These polymers are describedmore fully in U.S. patent application Ser. No. 09/044,798, filed Mar.20, 1998, which is incorporated herein by reference.

[0107] The polymer may be present in the dielectric composition in apure or neat state (not mixed with any solvents) or it may be present ina solution where it is mixed with solvents. When solvents are present,the polymer is preferably present in an amount of from about 1% to about50% by weight of the polymer, more preferably from about 3% to about20%. The solvent component is preferably present in an amount of fromabout 50% to about 99% by weight of the dielectric composition, morepreferably from about 80% to about 97%. Suitable solvents nonexclusivelyinclude aprotic solvents such as cyclic ketones includingcyclopentanone, cyclohexanone, cyclohexanone and cyclooctanone; cyclicamides such as N-alkylpyrrolidinone wherein the alkyl group has from 1to about 4 carbon atoms, and N-cyclohexyl-pyrrolidinone, and mixturesthereof.

[0108] Once formed, the dielectric composition is deposited onto asuitable substrate to thereby form a polymer layer on the substrate.Deposition may be conducted via conventional spin-coating, dip coating,roller coating, spraying, chemical vapor deposition methods, or meniscuscoating methods which are well-known in the art. Spin coating is mostpreferred. The thickness of the polymer layer on the substrate may varydepending on the deposition procedure and parameter setup, but typicallythe thickness may range from about 500 Å to about 50,000 Å, andpreferably from about 2000 Å to about 12000 Å. The amount of dielectriccomposition applied to the substrate may vary from about 1 ml to about10 ml, and preferably from about 2 ml to about 8 ml. In the preferredembodiment, the liquid dielectric composition is spun onto the uppersurface the substrate according to known spin techniques. Preferably,the polymer layer is applied by centrally applying the liquid dielectriccomposition to the substrate and then spinning the substrate on arotating wheel at speeds ranging from about 500 to about 6000 rpm,preferably from about 1500 to about 4000 rpm, for about 5 to about 60seconds, preferably from about 10 to about 30 seconds, in order tospread the solution evenly across the substrate surface. The polymerlayer preferably has a density of from about 1 g/cm³ to about 3 g/cm³.

[0109] The dielectric layer may optionally be heated to expel residualsolvent or to increase its molecular weight. The heating may beconducted by conventional means such as heating on a hot plate in air orin an inert atmosphere, or it may occur in a furnace or oven in air, orin an inert atmosphere, or it may occur in a vacuum furnace or vacuumoven. Heating is preferably conducted at a temperature of from about 80°C. to about 500° C., and more preferably from about 150° C. to about425° C. This heating is preferably performed from about 1 minute toabout 360 minutes, and more preferably from about 2 to about 60 minutes.The polymer layer may also optionally be exposed to actinic light, suchas UV light, to increase its molecular weight. The amount of exposuremay range from about 100 mJ/cm² to about 300 mJ/cm². The dielectriclayers may optionally be cured by overall exposed to electron beamradiation. Electron beam exposure may be controlled by setting the beamacceleration. Electron beam radiation may take place in any chamberhaving a means for providing electron beam radiation to substratesplaced therein. It is preferred that the electron beam exposing step isconducted with a wide, large beam of electron radiation from alarge-area electron beam source. Preferably, an electron beam chamber isused which provides a large area electron source. Suitable electron beamchambers are commercially available from Electron Vision, a unit ofAlliedSignal Inc., under the trade name ElectronCure™”. The principlesof operation and performance characteristics of such device aredescribed in U.S. Pat. No. 5,001,178, the disclosure of which isincorporated herein by reference. The temperature of the electron beamexposure preferably ranges from about 20° C. to about 450° C., morepreferably from about 50° C. to about 400° C. and most preferably fromabout 200° C. to about 400° C. The electron beam energy is preferablyfrom about 0.5 KeV to about 30 KeV, and more preferably from about 3 toabout 10 KeV. The dose of electrons is preferably from about 1 to about50,000 μC/cm² and more preferably from about 50 to about 20,000 μC/cm².The gas ambient in the electron beam tool can be any of the followinggases: nitrogen, oxygen, hydrogen, argon, a blend of hydrogen andnitrogen, ammonia, xenon or any combination of these gases. The electronbeam current is preferably from about 1 to about 40 mA, and morepreferably from about 5 to about 20 mA. Preferably, the electron beamexposing step is conducted with a wide, large beam of electron beamradiation from a uniform large-are electron beam source which covers anarea of from about 4 inches to about 256 square inches.

[0110] Vias are formed in the inorganic dielectric layer by well knownphotolithographic techniques using a photoresist composition. FIG. 4shows the coated substrate after step 4, i.e. imagewise patterning andremoval of portions of the resist and step 5, an inorganic dielectricetch to form cavities through these layers. Such are formed in a mannerwell known in the art such as by coating the photoresist, imagewiseexposing to actinic radiation such as through a suitable mask,developing the photoresist and etching away portions of the inorganicdielectric to form cavities. The photoresist composition may be positiveworking or negative working and are generally commercially available.Suitable positive working photoresists are well known in the art and maycomprise an o-quinone diazide radiation sensitizer. The o-quinonediazide sensitizers include the o-quinone-4-or-5-sulfonyl-diazidesdisclosed in U.S. Pat. Nos. 2,797,213; 3,106,465; 3,148,983; 3,130,047;3,201,329; 3,785,825; and 3,802,885. When o-quinone diazides are used,preferred binding resins include a water insoluble, aqueous alkalinesoluble or swellable binding resin, which is preferably a novolak.Suitable positive photodielectric resins may be obtained commercially,for example, under the trade name of AZ-P4620 from Clariant Corporationof Somerville, N.J. The photoresist is then imagewise exposed to actinicradiation such as light in the visible, ultraviolet or infrared regionsof the spectrum through a mask, or scanned by an electron beam, ion orneutron beam or X-ray radiation. Actinic radiation may be in the form ofincoherent light or coherent light, for example, light from a laser. Thephotoresist is then imagewise developed using a suitable solvent, suchas an aqueous alkaline solution. Optionally the photoresist is heated tocure the image portions thereof and thereafter developed to remove thenonimage portions and define a via mask. Vias are then formed by etchingtechniques which are well known in the art. Next the photoresist iscompletely removed from the inorganic dielectric surface by plasmaetching. Plasma generators which are capable of such etching aredescribed in U.S. Pat. Nos. 5,174,856 and 5,200,031.

[0111] Next, in a sixth step, the organic low-k dielectric is etched byan etch chemistry which does not remove the inorganic low-k dielectric.The resulting structure with vias is shown in FIG. 5. Next, a resistapplication step 7 is required for metal trench patterning. Anotherphotoresist is applied to the top of the inorganic dielectric layer andfills the vias in the organic dielectric layer and the inorganicdielectric layer with photoresist. FIG. 6 shows the structure afterapplication and baking of the layer of resist material. In an eighthstep, one imagewise exposes the resist through a metal trench mask,imagewise removes a portion of the photoresist from the top of theinorganic dielectric layer; and removes a portion and leaves a portionof the photoresist through a thickness of the inorganic dielectriclayer. The result is seen in FIG. 7.

[0112] A ninth step requires removing part of the inorganic dielectriclayer underlying the portions of the photoresist removed from the top ofthe inorganic dielectric layer to form trenches in the inorganicdielectric layer. Due to chemical differences between the inorganic andorganic dielectrics, the plasma etch rate of low-k organic dielectriccan be made to be significantly less than the plasma etch rate of theinorganic dielectric. As a result, the etch stops once the inorganicdielectric on top of the organic dielectric is cleared. No etchstop isrequired in this approach. The result is seen in FIG. 8.

[0113] The next step 10 removes the balance of the photoresist from thetop of the inorganic dielectric layer and from the vias and the resultis shown in FIG. 9. Step 11 fills the vias in the organic dielectric andthe trenches in the inorganic dielectric with a metal as seen in FIG.10. Suitable metals include aluminum, aluminum alloys, copper, copperalloys, tantalum, tungsten, titanium or other metals or mixtures thereofas typically employed in the formation of microelectronic devices. Themetal may be applied by such techniques as vapor deposition, sputtering,evaporation and the like. Copper is most preferred. The thickness of themetal layers is preferably from about 3,000 to 15,000 Angstroms.Typically the metal is applied by first forming a barrier metal seedinglayer on the walls of the vias and the top dielectric. Then the balanceof the metal is applied. As used herein, the term “metal” includesamalgams of metals. A barrier metal serves to prevent diffusion of theconductive metal into the dielectric layers. The barrier metal may be,for example, Ti or a nitride such TaN or TiN. Copper interconnectprocessing is used to form a self-aligned metal barrier on the top ofthe copper interconnect. With a metal barrier on top, the commonly usedsilicon nitride barrier is not necessary. It is to be understood thatthese steps may be repeated to provide a series of suitable layers andconductive paths over one another on the substrate to produce thearchitecture of FIG. 1. The architecture shown in FIG. 1 has severaldistinct features. A separation is not needed between two adjacent IMD.When separation layers are required, low-k dielectric films can be usedwith the approach taken in this invention which utilizes two dissimilarlow-k dielectric films for IMD (FIG. 2). In a conventional approach, CVDoxide or silicon nitride is commonly used as separation layer. Boththese prior inorganic dielectrics have the major disadvantage of havinga high dielectric constant, 4 and 7, respectively, for silicon oxide andsilicon nitride. Concerning the functions of the separation layers,heretofore a high dielectric constant material such as silicon nitride,is provided as an etchstop in opening metal trenches. In architecture I,there is no need to have such an etchstop since the organic low-kdielectric used for via-level IMD etches much slower than the inorganiclow-k dielectric and thus it is an etchstop by itself.

[0114] Separation layers are also used as an etchstop in openingborderless vias when the vias are misaligned to the underlying metalline. The presence of the separation layers can prevent the creation ofdeep and narrow trenches, which are a major yield and reliabilityconcern. However, a separation layer is not required for this inventionfor the reason that two dissimilar dielectrics are used and they aresignificantly different in their plasma etch characteristics. Thisembodiment has distinct advantages. Vias are not enlarged when a metaltrench mask is misaligned in the direction away from the underlying viaas shown in FIGS. 7-10. There is an issue of partially landed vias whena via is over-sized and/or misaligned to the underlying metal line asshown in FIG. 1. In the conventional approach, via over-sizing can beprevented by the addition of a separation layer between the adjacentIMD. Such a separation layer is not required in this embodiment due tothe fact that there is an extremely high plasma etch selectivity betweeninorganic and organic dielectrics in metal trench etching. Anotheradvantage of this embodiment is its compatibility with borderless vias.There are two vias shown in FIG. 1. The bottom of these vias is notfully landed on the underlying Cu lines. This results from the use ofborderless vias when they are misaligned in the direction away frommetal lines. Prior efforts have been made to prevent the creation ofdeep and narrow trenches at the bottom of partially landed via. In theconventional approach, an etchstop layer, such as silicon nitride, isoften added to prevent the formation of undesirable trenches. However,an etchstop is not necessary in this embodiment since there is asignificantly high plasma etch selectivity between organic and inorganicdielectrics in opening vias.

[0115] When it is impractical to remove resist selectively in thepresence of organic dielectrics, a different architecture, architectureII, is used. The following embodiments are to construct architecture IIas shown in FIG. 2. Architecture II differs from architecture I in thatthe former has separation layers between metal-level and via-level IMD.

[0116] A second embodiment of the invention is represented by theprocess steps shown in FIGS. 11-18. The process flow commences after theformation of a first level interconnect or Metal 1 as shown in FIG. 2.The process flow covers from Via 1 level through the second level ofinterconnect or Metal 2. However, the same processing steps can berepeated again for upper levels of vias and interconnects. The samesubstrate, organic dielectric and inorganic dielectric materials may beused as in embodiment 1. FIG. 11 shows the formation process for asecond embodiment of the invention. One begins with a substrate, whichcomprises a pattern of metal lines on the substrate and a dielectric onthe substrate between the metal lines as with embodiment 1. An organiclow-k dielectric is then deposited onto the substrate followed bydeposition of a thin inorganic low-k dielectric and spin-on and bakingof a photoresist. The resist is imagewise patterned and removed bydevelopment and a portion of the thin inorganic dielectric layer isremoved by etching thus defining vias through the thin inorganicdielectric layer. FIG. 12 shows the formation after via mask and resistdevelopment and inorganic low-k dielectric etch. FIG. 13 shows theprocess after resist removal. Some of the exposed part of the organiclow-k dielectric will usually be removed to a limited extent. However,such is not critical since the part of organic dielectric which is notcovered by a thin layer of inorganic dielectric will be totally removedlater. Then a thin organic dielectric etchstop material layer isdeposited on the thin inorganic dielectric layer. This also fills thevias in the thin inorganic dielectric layer with the organic dielectricmaterial. Then a metal level inorganic dielectric layer is deposited onthe organic dielectric etchstop layer. The metal level inorganicdielectric is then imagewise patterned. This may be done by depositing,baking, exposing and developing a photoresist. FIG. 14 shows the processafter organic low-k dielectric deposition, inorganic low-k dielectricdeposition, resist spin and bake and metal trench mask and resistdevelopment. This inorganic low-k dielectric layer is for metal-levelIMD. The portion of the inorganic dielectric layer under the removedpart of the photoresist is then etched down to the organic dielectricetchstop material layer to form trenches in the metal level inorganicdielectric layer. The organic low-k dielectric serves as etchstop sinceit etches significantly slower than the inorganic low-k dielectric. FIG.15 shows the metal trenches produced at this step after inorganic low-kdielectric etch. The portion of the organic dielectric etchstop materiallayer underlying the corresponding removed portion of the metal levelinorganic dielectric is then removed by etching to form trenchestherein. At the same time the organic etchstop material is removed fromthe vias in the thin inorganic dielectric layer. Some resist is removedat this step. FIG. 16 shows the process after the organic low-kdielectric etch step. Then one removes the portion of the organic vialevel dielectric layer underlying the thin inorganic dielectric layerthus forming vias through the organic via level dielectric layer down tothe metal lines. The inorganic low-k dielectric on top of the organiclow-k dielectric serves as mask. Resist is also removed at this step.Steps 12 and 13 can be combined together into a single step. The resultis shown in FIG. 17. Thereafter the vias are filled with a metal in thevia level organic dielectric layer and the thin inorganic dielectriclayer, and trenches in the organic dielectric etchstop layer and metallevel inorganic dielectric layer with a metal as shown in FIG. 18.Repetition of the process produces the structure of architecture II asseen in FIG. 2.

[0117] A third embodiment of the invention is represented by the processsteps shown in FIGS. 19-27. The process flow after the formation of thefirst-level interconnect or Metal 1. The process flow covers from Via 1level through the second□evel of interconnect or Metal 2. However, thesame processing steps can be repeated again for upper levels of vias andinterconnects. In this embodiment one providing a substrate, whichcomprises a pattern of metal lines on the substrate and a dielectric onthe substrate between the metal lines as with the previous embodiments.An organic via level dielectric layer is deposited on the substrate; athin inorganic dielectric layer is deposited on the organic via leveldielectric and a thin organic dielectric etchstop material layer isdeposited on the thin inorganic dielectric layer. The thin organicdielectric etchstop material layer and the thin inorganic low-kdielectric layer together separate the via-level and metal-level IMD.Then a metal level inorganic dielectric layer is deposited on theorganic dielectric etchstop layer. A photoresist is deposited on themetal level inorganic dielectric layer to produce the structure of FIG.19. The photoresist is imagewise exposed, baked and developed as before.After removing a portion of the metal level inorganic dielectric layerdown to the organic dielectric etchstop material layer vias are formedin the metal level inorganic dielectric layer as shown in FIG. 20. Afterremoving the portion of the organic dielectric etchstop material layerunderlying the corresponding removed portions of the metal levelinorganic dielectric layer vias are formed in the organic dielectricetchstop material layer. After removing the portion of the thininorganic dielectric layer underlying the corresponding removed portionsof the organic dielectric etchstop material layer vias are formed in thethin inorganic dielectric layer. The result is seen in FIG. 21. Theresist is then removed to provide the structure of FIG. 22. One thencovers the top of the metal level inorganic dielectric layer with aphotoresist and fills the vias in the metal level inorganic dielectriclayer, the organic dielectric etchstop material layer and the thininorganic dielectric layer with photoresist as shown in FIG. 23. Afterimagewise patterning the photoresist through a trench mask, removing aportion of the photoresist from the top of the metal level inorganicdielectric layer, and removing a portion and leaving a portion of thephotoresist through a thickness of the metal level inorganic dielectriclayer, the structure of FIG. 24 is obtained.

[0118] After removing part of the metal level inorganic dielectric layerunderlying the portions of the photoresist removed from the top of theinorganic dielectric layer trenches are formed in the metal levelinorganic dielectric layer as shown in FIG. 25. After removing thebalance of the photoresist from the top of the metal level inorganicdielectric layer and from the vias; and removing the portion of theorganic dielectric etchstop material layer underlying the trenches untilthe thin inorganic dielectric layer is reached, the structure of FIG. 26is obtained. One then removes the portion of the organic via leveldielectric layer underlying the vias in the thin inorganic dielectriclayer as shown in FIG. 27. This step completes the opening of via holes.After filling the vias in the via level organic dielectric layer and thethin inorganic dielectric layer, and trenches in the organic dielectricetchstop layer and metal level inorganic dielectric layer with a metalthe structure of FIG. 18 is obtained. The process may be repeated toobtain architecture II of FIG. 2. The third embodiment differs from thesecond embodiment in that all dielectric depositions are donesequentially and no masking and plasma etch is done between dielectricdepositions. All masking and etches are done sequentially. This mayrepresent a preferred process flow in certain integrated circuitfabrication facilities.

[0119] A fourth embodiment of the invention is represented by theprocess steps shown in FIGS. 28-32. The process flow commences after theformation of the first-level interconnect or Metal 1. The process flowcovers from Via 1 level through the second level of interconnect orMetal 2. However, the same processing steps can be repeated again forupper levels of vias and interconnects. Steps 1-9 for this fourthembodiment are the same as steps 1-9 of the third embodiment as shown inFIGS. 19-21 as described above. One then removes the portion of theorganic via level dielectric layer underlying the corresponding removedportions of the thin inorganic dielectric layer to form vias in theorganic via level dielectric layer as shown in FIG. 28. One then coversthe top of the metal level inorganic dielectric layer with a photoresistand fills the vias in the metal level inorganic dielectric layer, theorganic dielectric etchstop material layer, the thin inorganicdielectric layer and the organic via level dielectric layer withphotoresist as shown in FIG. 29.

[0120] After imagewise patterning and removing a portion of thephotoresist from the top of the inorganic dielectric layer; and removinga portion and leaving a portion of the photoresist through a thicknessof the metal level inorganic dielectric layer the structure of FIG. 30is obtained. After removing part of the metal level inorganic dielectriclayer underlying the portions of the photoresist removed from the top ofthe inorganic dielectric layer trenches are formed in the metal levelinorganic dielectric layer as shown in FIG. 31. Thereafter one removesthe balance of the photoresist from the top of the metal level inorganicdielectric layer and from the vias; and removes the portion of theorganic dielectric etchstop material layer underlying the trenches untilthe thin inorganic dielectric layer is reached as shown in FIG. 32.After filling the vias in the via level organic dielectric layer and thethin inorganic dielectric layer, and trenches in the organic dielectricetchstop layer and metal level inorganic dielectric layer with a metalthe structure of FIG. 18 is obtained. Upon repetition of these steps,the architecture of FIG. 2 is obtained. Embodiment four is unique inthat via patterning is entirely independent of metal trench patterning.

[0121] While the present invention has been particularly shown anddescribed with reference to preferred embodiments, it will be readilyappreciated by those of ordinary skill in the art that various changesand modifications may be made without departing from the spirit andscope of the invention. It is intended that the claims be to interpretedto cover the disclosed embodiment, those alternatives which have beendiscussed above and all equivalents thereto.

1. An integrated circuit structure which comprises a substrate and (a) an inorganic layer on the substrate which comprises a pattern of metal lines on the substrate and an inorganic dielectric on the substrate between the metal lines; and (b) an organic layer on the inorganic layer which comprises an organic dielectric having metal filled vias therethrough which connect to the metal lines of the inorganic layer.
 2. The integrated circuit structure of claim 1 which comprises (c) an additional inorganic layer on the organic layer which comprises a pattern of additional metal lines on the organic layer and an inorganic dielectric on the organic layer between the additional metal lines; and (d) an additional organic layer on the additional inorganic layer which comprises an organic dielectric having metal filled vias therethrough which connect to the additional metal lines of the additional inorganic layer.
 3. The integrated circuit structure of claim 2 which comprises one or more further alternating inorganic layers (c) and organic layers (d) on the additional inorganic layer (c) and organic layer (d).
 4. The integrated circuit structure of claim 2 further comprising an inorganic dielectric layer on the organic layer between the vias and under the additional metal lines of the additional inorganic layer; and an organic dielectric on the inorganic dielectric layer between the additional metal lines of the additional inorganic layer.
 5. The integrated circuit structure of claim 3 further comprising an inorganic dielectric layer on each alternating organic layer (d) between the vias and under the additional metal lines of the alternating inorganic layer; and an organic dielectric on the inorganic dielectric layer between the additional metal lines of the additional inorganic layer.
 6. The integrated circuit structure of claim 1 wherein the metal lines and vias have a barrier metal on one or more edges thereof.
 7. An integrated circuit structure produced according to a process which comprises (a) providing a substrate which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines; (b) depositing an organic dielectric layer on the substrate; (c) depositing an inorganic dielectric layer on the organic dielectric layer; (d) etching a pattern of vias through the inorganic dielectric layer; (e) etching a pattern of vias through the organic dielectric layer which correspond to the pattern of vias through the inorganic dielectric layer; (f) applying a photoresist to the top of the inorganic dielectric layer and filling the vias in the organic dielectric layer and the inorganic dielectric layer with photoresist; (g) imagewise removing a portion of the photoresist from the top of the inorganic dielectric layer; and removing a portion and leaving a portion of the photoresist through a thickness of the inorganic dielectric layer; (h) removing part of the inorganic dielectric layer underlying the portions of the photoresist removed from the top of the inorganic dielectric layer to form trenches in the inorganic dielectric layer; (i) removing the balance of the photoresist from the top of the inorganic dielectric layer and from the vias; (j) filling the vias in the organic dielectric and the trenches in the inorganic dielectric with a metal.
 8. The integrated circuit structure produced according to claim 7 wherein steps (b) through (j) are repeated at least once on the previously formed integrated circuit structure. 9-10. (Canceled)
 11. An integrated circuit structure produced according to a process which comprises (a) providing a substrate, which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines; (b) depositing an organic via level dielectric on the substrate; (c) depositing an thin inorganic dielectric layer on the organic via level dielectric; (d) imagewise patterning and removing a portion of the thin inorganic dielectric layer thus defining vias through the thin inorganic dielectric layer; (e) depositing a thin organic dielectric etchstop material layer on the thin inorganic dielectric layer and filling the vias in the thin inorganic dielectric layer with the organic dielectric material; (f) depositing a metal level inorganic dielectric layer on the organic dielectric etchstop layer; (g) imagewise patterning and removing a portion of the metal level inorganic dielectric layer down to the organic dielectric etchstop material layer to form trenches in the metal level inorganic dielectric layer; (h) removing the portion of the organic dielectric etchstop material layer underlying the corresponding removed portion of the metal level inorganic dielectric to form trenches therein, and removing the organic etchstop material from the vias in the thin inorganic dielectric layer; (i) removing the portion of the organic via level dielectric layer underlying the thin inorganic dielectric layer thus forming vias through the organic via level dielectric layer down to the metal lines; (j) filling the vias in the via level organic dielectric layer and the thin inorganic dielectric layer, and trenches in the organic dielectric etchstop layer and metal level inorganic dielectric layer with a metal.
 12. The integrated circuit structure produced according to claim 11 wherein steps (b) through (j) are repeated at least once on the previously formed integrated circuit structure. 13-14. (Canceled)
 15. An integrated circuit structure produced according to a process which comprises (a) providing a substrate, which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines; (b) depositing an organic via level dielectric layer on the substrate; (c) depositing an thin inorganic dielectric layer on the organic via level dielectric; (d) depositing a thin organic dielectric etchstop material layer on the thin inorganic dielectric layer; (e) depositing a metal level inorganic dielectric layer on the organic dielectric etchstop layer; (f) imagewise patterning and removing a portion of the metal level inorganic dielectric layer down to the organic dielectric etchstop material layer to form vias in the metal level inorganic dielectric layer; (g) removing the portion of the organic dielectric etchstop material layer underlying the corresponding removed portions of the metal level inorganic dielectric layer to form vias in the organic dielectric etchstop material layer; (h) removing the portion of the thin inorganic dielectric layer underlying the corresponding removed portions of the organic dielectric etchstop material layer to form vias in the thin inorganic dielectric layer; (i) covering the top of the metal level inorganic dielectric layer with a photoresist and filling the vias in the metal level inorganic dielectric layer, the organic dielectric etchstop material layer and the thin inorganic dielectric layer with photoresist; (j) imagewise patterning and removing a portion of the photoresist from the top of the metal level inorganic dielectric layer; and removing a portion and leaving a portion of the photoresist through a thickness of the metal level inorganic dielectric layer; (k) removing part of the metal level inorganic dielectric layer underlying the portions of the photoresist removed from the top of the inorganic dielectric layer to form trenches in the metal level inorganic dielectric layer; (l) removing the balance of the photoresist from the top of the metal level inorganic dielectric layer and from the vias; and removing the portion of the organic dielectric etchstop material layer underlying the trenches until the thin inorganic dielectric layer is reached; (m) removing the portion of the organic via level dielectric layer underlying the vias in the thin inorganic dielectric layer; (n) filling the vias in the via level organic dielectric layer and the thin inorganic dielectric layer, and trenches in the organic dielectric etchstop layer and metal level inorganic dielectric layer with a metal.
 16. The integrated circuit structure produced according to claim 15 wherein steps (b) through (n) are repeated at least once on the previously formed integrated circuit structure. 17-18. (Canceled)
 19. An integrated circuit structure produced according to a process which comprises (a) providing a substrate, which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines; (b) depositing an organic via level dielectric layer on the substrate; (c) depositing an thin inorganic dielectric layer on the organic via level dielectric (d) depositing a thin organic dielectric etchstop material layer on the thin inorganic dielectric layer; (e) depositing a metal level inorganic dielectric layer on the organic dielectric etchstop layer; (f) imagewise patterning and removing a portion of the metal level inorganic dielectric layer down to the organic dielectric etchstop material layer to form vias in the metal level inorganic dielectric layer; (g) removing the portion of the organic dielectric etchstop material layer underlying the corresponding removed portions of the metal level inorganic dielectric layer to form vias in the organic dielectric etchstop material layer; (h) removing the portion of the thin inorganic dielectric layer underlying the corresponding removed portions of the organic dielectric etchstop material layer to form vias in the thin inorganic dielectric layer; (i) removing the portion of the organic via level dielectric layer underlying the corresponding removed portions of the thin inorganic dielectric layer to form vias in the organic via level dielectric layer; (j) covering the top of the metal level inorganic dielectric layer with a photoresist and filling the vias in the metal level inorganic dielectric layer, the organic dielectric etchstop material layer, the thin inorganic dielectric layer and the organic via level dielectric layer with photoresist; (k) imagewise patterning and removing a portion of the photoresist from the top of the inorganic dielectric layer; and removing a portion and leaving a portion of the photoresist through a thickness of the metal level inorganic dielectric layer; (l) removing part of the metal level inorganic dielectric layer underlying the portions of the photoresist removed from the top of the inorganic dielectric layer to form trenches in the metal level inorganic dielectric layer; (m) removing the balance of the photoresist from the top of the metal level inorganic dielectric layer and from the vias; and removing the portion of the organic dielectric etchstop material layer underlying the trenches until the thin inorganic dielectric layer is reached; (n) filling the vias in the via level organic dielectric layer and the thin inorganic dielectric layer, and trenches in the organic dielectric etchstop layer and metal level inorganic dielectric layer with a metal.
 20. The integrated circuit structure produced according to claim 19 wherein steps (b) through (n) are repeated at least once on the previously formed integrated circuit structure. 21-31. (Canceled)
 32. The integrated circuit structure of claim 1 wherein the organic layer comprises a dielectric selected from the group consisting of alkoxysilane polymers, organic siloxanes, hydroorganosiloxanes, hydrogenmethylsilsesquioxane, hydrogenethylsilsesquioxane, hydrogenpropylsilsesquioxane, hydrogenbutylsilsesquioxane, hydrogentert-butylsilsesquioxane and hydrogenphenylsilsesquioxane, methylated siloxane polymers; polymers having the formulae [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n), [(HSiO_(1.5))_(x)(RSiO_(1.5))_(y)]_(n) and [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n) wherein x=about 6 to about 20, y=1 to about 3, z=about 6 to about 20, n=1 to about 4,000, and each R is independently C₁ to C₈ alkyl or C₆ to C₁₂ aryl; organic silicon containing polymers having the formulae [H—SiO_(1.5)]_(n)[R—SiO_(1.5)]_(m), [H_(0.4)—SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)—SiO_(1.5-1.8)]_(m), [H_(0-1.0)—SiO_(1.5-2.0)]_(n)[R—SiO_(1.5)]_(m), [H—SiO_(1.5)]_(x)[R—SiO_(1.5)]_(y)[SiO₂]_(z), wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof; the sum of n and m, or the sum or x, y and z is from about 8 to about 5000, and m and y are selected such that carbon containing substituents are present in an amount of less than about 40 Mole percent; organic silicon containing polymers having the formulae: [HSiO_(1.5)]_(n)[RSiO_(1.5)]_(m), [H_(0.4-1.0)SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)SiO_(1.5-1.8)]_(m), [H_(0-1.0)SiO_(1.5-2.0)]_(n)[RSiO_(1.5)]_(m), wherein the sum of n and m is from about 8 to about 5000 and m is selected such that the carbon containing substituent is present in an amount of from about 40 mole percent or greater; and [HSiO_(1.5)]_(x)[RSiO_(1.5)]_(y)[SiO₂]_(z); wherein the sum of x, y and z is from about 8 to about 5000 and y is selected such that the carbon containing substituent is present in an amount of about 40 mole % or greater; and wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof, and mixtures thereof; and wherein the inorganic layer comprises an inorganic dielectric selected from the group consisting of hydrogensiloxanes, inorganic hydrogensilsesquioxanes and combinations thereof; and wherein the hydrogensiloxanes have the formula [(HSiO_(1.5))_(n)O_(y)]_(n), and the hydrogensilsesquioxanes have the formula (HSiO_(1.5))_(n), wherein x=about 6 to about 20, y=1 to about 3, and n=1 to about 4,000.
 33. The integrated circuit structure of claim 7 wherein the organic dielectric layer comprises an organic dielectric selected from the group consisting of alkoxysilane polymers, organic siloxanes, hydroorganosiloxanes, hydrogenmethylsilsesquioxane, hydrogenethylsilsesquioxane, hydrogenpropylsilsesquioxane, hydrogenbutylsilsesquioxane, hydrogentert-butylsilsesquioxane and hydrogenphenylsilsesquioxane, methylated siloxane polymers; polymers having the formulae [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n), [(HSiO_(1.5))_(x)(RSiO_(1.5))_(y)]_(n) and [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n) wherein x=about 6 to about 20, y=1 to about 3, z=about 6 to about 20, n=1 to about 4,000, and each R is independently C₁ to C₈ alkyl or C₆ to C₁₂ aryl; organic silicon containing polymers having the formulae [H—SiO_(1.5)]_(n)[R—SiO_(1.5)]_(m), [H_(0.4)—SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)—SiO_(1.5-1.8)]_(m), [H_(0-1.0)—SiO_(1.5-2.0)]_(n)[R—SiO_(1.5)]_(m), [H—SiO_(1.5)]_(x)[R—SiO_(1.5)]_(y)[SiO₂]_(z), wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof; the sum of n and m, or the sum or x, y and z is from about 8 to about 5000, and m and y are selected such that carbon containing substituents are present in an amount of less than about 40 Mole percent; organic silicon containing polymers having the formulae: [HSiO_(1.5)]_(n)[RSiO_(1.5)]_(m), [H_(0.4-1.0)SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)SiO_(1.5-1.8]) _(m), [H_(0-1.0)SiO_(1.5-2.0)]_(n)[RSiO_(1.5)]_(m), wherein the sum of n and m is from about 8 to about 5000 and m is selected such that the carbon containing substituent is present in an amount of from about 40 mole percent or greater; and [HSiO_(1.5)]_(x)[RSiO_(1.5)]_(y)[SiO₂]_(z); wherein the sum of x, y and z is from about 8 to about 5000 and y is selected such that the carbon containing substituent is present in an amount of about 40 mole % or greater; and wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof, and mixtures thereof; and wherein the inorganic dielectric layer comprises an inorganic dielectric selected from the group consisting of hydrogensiloxanes, inorganic hydrogensilsesquioxanes and combinations thereof; and wherein the hydrogensiloxanes have the formula [(HSiO_(1.5))_(x)O_(y)]_(n), and the hydrogensilsesquioxanes have the formula (HSiO_(1.5))_(n), wherein x=about 6 to about 20, y=1 to about 3, and n=1 to about 4,000.
 34. The integrated circuit structure of claim 11 wherein the organic via level dielectric comprises an organic dielectric selected from the group consisting of alkoxysilane polymers, organic siloxanes, hydroorganosiloxanes, hydrogenmethylsilsesquioxane, hydrogenethylsilsesquioxane, hydrogenpropylsilsesquioxane, hydrogenbutylsilsesquioxane, hydrogentert-butylsilsesquioxane and hydrogenphenylsilsesquioxane, methylated siloxane polymers; polymers having the formulae [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n), [(HSiO_(1.5))_(x)(RSiO_(1.5))_(y)]_(n) and [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n) wherein x=about 6 to about 20, y=1 to about 3, z=about 6 to about 20, n=1 to about 4,000, and each R is independently C_(1 to C) ₈ alkyl or C₆ to C₁₂ aryl; organic silicon containing polymers having the formulae [H—SiO_(1.5)]_(n)[R—SiO_(1.5)]_(m), [H_(0.4)—SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)—SiO_(1.5-1.8)]_(m), [H_(0-1.0)—SiO_(1.5-2.0)]_(n)[R—SiO_(1.5)]_(m), [H—SiO_(1.5)]_(x)[R—SiO_(1.5)]_(y)[SiO₂]_(z), wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof; the sum of n and m, or the sum or x, y and z is from about 8 to about 5000, and m and y are selected such that carbon containing substituents are present in an amount of less than about 40 Mole percent; organic silicon containing polymers having the formulae: [HSiO_(1.5)]_(n)[RSiO_(1.5)]_(m), [H_(0.4-1.0)SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)SiO_(1.5-1.8)]_(m), [H_(0-1.0)SiO_(1.5-2.0)]_(n)[RSiO_(1.5)]_(m), wherein the sum of n and m is from about 8 to about 5000 and m is selected such that the carbon containing substituent is present in an amount of from about 40 mole percent or greater; and [HSiO_(1.5)]_(x)[RSiO_(1.5)]_(y)[SiO₂]_(z); wherein the sum of x, y and z is from about 8 to about 5000 and y is selected such that the carbon containing substituent is present in an amount of about 40 mole % or greater; and wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof, and mixtures thereof; and wherein the inorganic dielectric layer comprises an inorganic dielectric selected from the group consisting of hydrogensiloxanes, inorganic hydrogensilsesquioxanes and combinations thereof; and wherein the hydrogensiloxanes have the formula [(HSiO_(1.5))_(x)O_(y)]_(n), and the hydrogensilsesquioxanes have the formula (HSiO_(1.5))_(n), wherein x=about 6 to about 20, y=1 to about 3, and n=1 to about 4,000.
 35. The integrated circuit structure of claim 15 wherein the organic via level dielectric comprises an organic dielectric selected from the group consisting of alkoxysilane polymers, organic siloxanes, hydroorganosiloxanes, hydrogenmethylsilsesquioxane, hydrogenethylsilsesquioxane, hydrogenpropylsilsesquioxane, hydrogenbutylsilsesquioxane, hydrogentert-butylsilsesquioxane and hydrogenphenylsilsesquioxane, methylated siloxane polymers; polymers having the formulae [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n), [(HSiO_(1.5))_(x)(RSiO_(1.5))_(y)]_(n) and [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n) wherein x=about 6 to about 20, y=1 to about 3, z=about 6 to about 20, n=1 to about 4,000, and each R is independently C₁ to C₈ alkyl or C₆ to C₁₂ aryl; organic silicon containing polymers having the formulae [H—SiO_(1.5)]_(n)[R—SiO_(1.5)]_(m), [H_(0.4)—SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)—SiO_(1.5-1.8)]_(m), [H_(0-1.0)—SiO_(1.5-2.0)]_(n)[R—SiO_(1.5)]_(m), [H—SiO_(1.5)]_(x)[R—SiO_(1.5)]_(y)[SiO₂]_(z), wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof; the sum of n and m, or the sum or x, y and z is from about 8 to about 5000, and m and y are selected such that carbon containing substituents are present in an amount of less than about 40 Mole percent; organic silicon containing polymers having the formulae: [HSiO_(1.5)]_(n)[RSiO_(1.5)]_(m), [H_(0.4-1.0)SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)SiO_(1.5-1.8)]_(m), [H_(0-1.0)SiO_(1.5-2.0)]_(n)[RSiO_(1.5)]_(m), wherein the sum of n and m is from about 8 to about 5000 and m is selected such that the carbon containing substituent is present in an amount of from about 40 mole percent or greater; and [HSiO_(1.5)]_(x)[RSiO_(1.5)]_(y)[SiO₂]_(z); wherein the sum of x, y and z is from about 8 to about 5000 and y is selected such that the carbon containing substituent is present in an amount of about 40 mole % or greater; and wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof, and mixtures thereof; and wherein the inorganic dielectric layer comprises an inorganic dielectric selected from the group consisting of hydrogensiloxanes, inorganic hydrogensilsesquioxanes and combinations thereof; and wherein the hydrogensiloxanes have the formula [(HSiO_(1.5))_(x)O_(y)]_(n), and the hydrogensilsesquioxanes have the formula (HSiO_(1.5))_(n) wherein x=about 6 to about 20, y=1 to about 3, and n=1 to about 4,000.
 36. The integrated circuit structure of claim 19 wherein the organic via level dielectric comprises an organic dielectric selected from the group consisting of alkoxysilane polymers, organic siloxanes, hydroorganosiloxanes, hydrogenmethylsilsesquioxane, hydrogenethylsilsesquioxane, hydrogenpropylsilsesquioxane, hydrogenbutylsilsesquioxane, hydrogentert-butylsilsesquioxane and hydrogenphenylsilsesquioxane, methylated siloxane polymers; polymers having the formulae [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n), [(HSiO_(1.5))_(x)(RSiO_(1.5))_(y)]_(n) and [(HSiO_(1.5))_(x)O_(y)(RSiO_(1.5))_(z)]_(n) wherein x=about 6 to about 20, y=1 to about 3, z=about 6 to about 20, n=1 to about 4,000, and each R is independently C₁ to C₈ alkyl or C₆ to C₁₂ aryl; organic silicon containing polymers having the formulae [H—SiO_(1.5)]_(n)[R—SiO_(1.5)]_(m), [H_(0.4)—SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)—SiO_(1.5-1.8)]_(m), [H_(0-1.0)—SiO_(1.5-2.0)]_(n)[R—SiO_(1.5)]_(m), [H—SiO_(1.5)]_(x)[R—SiO_(1.5)]_(y)[SiO₂]_(z), wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof; the sum of n and m, or the sum or x, y and z is from about 8 to about 5000, and m and y are selected such that carbon containing substituents are present in an amount of less than about 40 Mole percent; organic silicon containing polymers having the formulae: [HSiO_(1.5)]_(n)[RSiO_(1.5)]_(m), [H_(0.4-1.0)SiO_(1.5-1.8)]_(n)[R_(0.4-1.0)SiO_(1.5-1.8)]_(m), [H_(0-1.0)SiO_(1.5-2.0)]_(n)[RSiO_(1.5)]_(m), wherein the sum of n and m is from about 8 to about 5000 and m is selected such that the carbon containing substituent is present in an amount of from about 40 mole percent or greater; and [HSiO_(1.5)]_(x)[RSiO_(1.5)]_(y)[SiO₂]_(z); wherein the sum of x, y and z is from about 8 to about 5000 and y is selected such that the carbon containing substituent is present in an amount of about 40 mole % or greater; and wherein R is selected from substituted and unsubstituted straight chain and branched alkyl groups, cycloalkyl groups, substituted and unsubstituted aryl groups, and mixtures thereof, and mixtures thereof; and wherein the inorganic dielectric layer comprises an inorganic dielectric selected from the group consisting of hydrogensiloxanes, inorganic hydrogensilsesquioxanes and combinations thereof; and wherein the hydrogensiloxanes have the formula [(HSiO_(1.5))_(x)O_(y)]_(n), and the hydrogensilsesquioxanes have the formula (HSiO_(1.5))_(n), wherein x=about 6 to about 20, y=1 to about 3, and n=1 to about 4,000. 